In the last blog, we have discussed the new material needs and challenges for the 3D packaging and fan-out wafer level packaging processes. 3D packaging process has been implemented by some applications such as memory chips, which don’t generate a lot of heat during processing. But when a logic chip is included in the 3D chip configuration, the heat generated becomes very difficult to manage and overheating often becomes a critical issue. The most popular 3D chip design at the present is top DRAM and bottom logic die. Further integration beyond the DRAM/Logic design would still be challenging to realize. There is a long way ahead for the semiconductor industry to fully adopt the 3D packaging process.
In this technology transition, what we see most is 2.5D packaging process. There are many different 2.5D packaging processes from different vendors. The term refers a family of IC chip packaging technologies that stack chips side-by-side on a passive interposer layer. Intel’s embedded multi-die interconnect bridge (EMIB) is a little different from the rest of the family but it should be classified as 2.5D packaging as well. The requirements for the RDL dielectrics from the 2.5D process may not be as demanding as a true 3D IC packaging. This is because the heat and material stress are easier to be managed in the current 2.5D IC configuration.
One thing to point out is that there has always been confusion about the term 2.5D IC, even for these who have worked in this field for many years. Some people just take 2.5D IC as a sub-class under the 3D IC, as may lead to even more confusion about the term. This argument around the coined 2.5D term is apparently not as important as the technology itself. I would agree with that the 2.5D IC represents a transitioning technology from the traditional 2D IC to 3D IC. Through silicon via (TSV) and interposer layer are two characteristics for a 2.5D IC process, in addition to the side-by-side multi-chip configuration. The 2.5D IC certainly shows great advantages for heat and stress management in comparison to the true 3D chip configuration. It may stay around for quite a long while before the true 3D IC is being fully implemented.