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  • Writer's pictureQingzhou Cui

Material Needs and Challenges for the Current Fan-out Wafer Level Packaging Process

Updated: Mar 29, 2020


Moore’s Law has guided semiconductor industry for the past 50 years, As the current front end process aims at scales of 10nm and below, the technical challenge has never been bigger. When further scaling is approaching to the physics and geometry limits at the present time, we are looking for alternative solutions to continue driving the modern digital revolution. Recent development of 3D packaging has demonstrated a key step towards a new “Beyond Moore’s” era. Instead of scaling down for individual transistors, extending the device to a third Z direction. One key enabling technology for 3D packaging is wafer level fan-out packaging process. The goal in 3D packaging is to realize chip-on-chip, chip-on-system, and system-on-system packaging.

As the 3D chip configuration is being implemented in near future, there are still some issues that we have to solve. For the critical fan-out wafer level packaging process, RDL layer metallization, molding compounds, and RDL dielectrics are the major material enablers. Especially, rerouting through RDL dielectric multi-layers is the key for the success of the process. However, there are two critical issues that we have to face when using polymers as permanent structural materials in the case. First, material stress and polymer intrinsic properties limit their capability to pass various reliability tests for this process. The coefficient of thermal expansion (CTE) mismatch among different materials would lead to wafer curvature and device stress. The wafer curvature greatly increases the difficulties for wafer alignment in later processing. The stress often lead to material cracks, failures, and various reliability issues over the life span of electronic devices. Polymers’ intrinsic properties such as viscoelastic behaviors and lacking of mechanical strength may also contribute to different reliability issues and reduce devices’ lifetime. Second, the thermal conductivity for polymers is usually low and thermal management becomes the key issue during the process of designing new chips and processes. As we pile up chips/dies in Z-direction, the heat generated from underneath chips, especially from a logic chip, is difficult to spread out and therefore often lead to device overheating and premature failures. Existed materials from the current market include low temp. PI, PBO, and BCB. They all have issues when used as dielectrics for the RDL layers. A new material is still in a great need for this booming sector of the current semiconductor industry. Polymer Solutions for Electronics Consulting will play active roles in searching for new "ideal" materials for the fan-out WLP and 3D packaging processes.


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